Package-on-package (PoP) technology is a 3D packaging technology in which packaged silicon die can be stacked on top of each other, for example as shown in FIG. 1. This technology can be used to reduce the overall size of a printed circuit board (PCB) and example applications include mobile telephones, where a memory chip may be mounted on top of a logic chip. FIG. 1 shows a schematic diagram of an example PoP in which a lower die 101 is mounted on a substrate 102 and an upper die 103 is mounted on a substrate 104. Each of these packaged die may be tested before the upper die 103 and substrate 104 are mounted on the lower substrate 102.
By using PoP technology the density of die on a PCB can be increased; however such packages are considerably bigger than the die themselves and there is a desire to reduce the overall size of packaged die further to enable enhanced integration and to use PCB space more efficiently. Moreover, increasing the package size to facilitate package-to-package connections increases the package cost, through increased material usage, and reduction of the number of packages in an assembly lot.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known packaging techniques.